1. Field of the Invention
The present invention relates to a semiconductor device of insulated gate type, which is particularly well suited for applications to a power MOS transistor, an IGBT and a thyristor.
2. Description of the Related Art
A planar type MOSFET, a V-groove type MOSFET and a trench type MOSFET have heretofore been known as power MOS transistors, which are shown in FIGS. 52A to 52C, respectively. The planar type MOSFET shown in FIG. 52A is such that a voltage is applied to a gate electrode 101, whereby a current is caused to flow in the lateral direction of a substrate with an inversion type channel being a surface part of a p-type base region 104 between an n-type source region 102 and an n-type drift region 103.
The V-groove type MOSFET shown in FIG. 52B is so constructed that a gate electrode 112 is arranged within a V-shaped groove 111. This V-groove type MOSFET operates similarly to the planar type MOSFET. Since, however, a p-type base region 113 sideward of the V-shaped groove 111 is used as an inversion type channel, a current comes to flow in a depth direction of a substrate. Accordingly, the substrate area of the V-groove type MOSFET required per cell can be reduced to decrease the ON resistance thereof, as compared with that of the planar type MOSFET.
The trench type MOSFET shown in FIG. 52C is so constructed that a gate electrode 122 is arranged within a groove 121 dug substantially perpendicularly to a substrate (Japanese Patent Application Laid-open No. 4-162572). This trench type MOSFET operates similarly to the V-groove type MOSFET. Since, however, the groove 121 is dug substantially perpendicularly to the substrate, the substrate area of the trench type MOSFET required per cell can be more reduced to decrease the ON resistance thereof still further, as compared with that of the V-groove type MOSFET.
In this manner, the decrease of the ON resistance has hitherto been attained by altering the construction wherein the channel region parallel to the surface of the substrate is formed as in the planar type MOSFET, into the construction wherein the channel region for causing the current to flow in the depth direction of the substrate is formed by digging the groove 111 or 121 in the substrate as in the V-groove type MOSFET or the trench type MOSFET.
It is desired, however, to decrease the ON resistance still further. In order to decrease the ON resistance, there has been proposed a method in which a channel region is formed, not only in a principal plane of a substrate, but also in a depth direction thereof. For example, the official gazettes of Japanese Patent Applications Laid-open No. 61-125174 and No. 8-204195 propose methods in each of which a gate is extended in a direction perpendicular to the principal surface of a substrate.
The former of these methods, however, is premised on a logic element which is of a structure having no drift layer, that is, which is not of a structure exhibiting a high withstand voltage, and which cannot be used as a power element. On the other hand, the latter produces a power element which has a semiconductor layer corresponding to a drift layer. Since, however, an insulated gate is formed both in a direction parallel to the principal plane of the semiconductor substrate and in the depth direction of the semiconductor substrate, an area of a source contact region in the principal surface of the substrate and that of a gate region along the principal plane of the substrate are restrained each other, to pose the problem that the restraint is disadvantageous for micrifying the element. Moreover, since individual impurity layers are formed by diffusion, the impurity layer of the channel region has a concentration distribution in the depth direction, and only that part of the channel region at which the gate threshold voltage becomes low functions as the very channel, to pose the problem that the substantial effect of decreasing the ON resistance is low.
Proposed in the official gazettes of Japanese Patent Application Laid-open No. 8-330601 is a semiconductor device in which two opposing trenches are formed in a substrate, and diffused layers (concretely, a base layer, a source layer and a drain layer) are formed so as to extend in the depth direction of the trenches by implanting ions obliquely to the sidewalls of the trenches, whereby the direction perpendicular to the principal surface of the substrate becomes the width direction of a gate. The schematic construction of the semiconductor device having the structure disclosed in this official gazette is shown in FIG. 53.
As shown in the figure, the semiconductor device disclosed in the official gazette is so constructed that the source layer 152 and the drain layer 153 are formed so as to extend along the inner walls of the corresponding trenches 150, that the base layer 151 is formed inside the source layer 152 as viewed from one of the trenches 150, and that a drift layer 154 is provided between the base layer 151 and the drain layer 152. Herein, although no illustration is made in the figure, the respective trenches 150 are filled up with insulating layers, whereby individual elements are isolated by the trenches.
In such a structure, however, concentration distributions are involved in the width directions of the diffused layers 151 to 153 (in a direction parallel to the principal surface of the substrate), and various problems arise.
For example, since the base layer 151 has the concentration distribution in the width direction, the internal resistance of this base layer 151 heightens to pose the problem that a parasitic n-p-n transistor which is constructed of the source layer 152, base layer 151 and drift layer 153 becomes liable to turn ON especially in a region which is deep from the principal surface of the substrate.
Moreover, since the base layer 151 has the concentration distribution in the width direction, a depletion layer becomes liable to elongate and to incur punch-through in a region of low concentration. When it is intended to prevent this drawback, the width of the base layer 151 must be enlarged correspondingly, to pose the problem that the larger width is disadvantageous for micrifying the element.
Further, when the source layer 152 and the drain layer 153 are deepened, the internal resistances thereof heighten in a series relation. Therefore, even when a channel resistance is lowered in a parallel relation with the spread of a channel width, the impedance of the whole element rises, and the normalized ON resistance thereof rises. In this regard, when the source layer 152 and the drain layer 153 have the concentration distributions in the width directions, the magnitudes of increases in the internal resistances enlarge, to pose the problem that the element cannot be formed down to a deep position.
Meanwhile, in the semiconductor device of the above structure, the diffused layers 751 to 153 are formed by the ion implantation oblique to the inner wall surfaces of the trenches 150, and various problems are caused by the oblique ion implantation. For example, the layout of the element must be designed with reference to the trenches 150. This poses the problem that the versatility of design lowers. Besides, the trenches 150 are filled up with the insulating layers after the formation of the diffused layers, thereby to use the trenches 150 for the element isolation. This poses the problem that the density of integration of the elements lowers correspondingly.
In view of the above, the present invention has for its object to decrease an ON resistance still further in a semiconductor device of insulated gate type.
According to one aspect of the present invention, a semiconductor device has a base region of a first conductivity type provided in a semiconductor substrate and extending from a principal surface of the semiconductor substrate in a first direction perpendicular to the principal surface; a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction; a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region; a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region; a trench dug from the principal surface and penetrating the base region from the source region in a second direction parallel to the principal surface; a gate insulating film provided on a surface of the trench; a gate electrode filling the trench through the gate insulating film; a source electrode electrically connected to the source region and the base region; and a drain electrode electrically connected to the drain region. The base region and the source region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction.
According to this construction, when a voltage is applied to the gate electrode, a channel region is formed in a portion of the base region adjoining the trench. The channel region has a channel width in the first direction, i.e., in a depth direction of the semiconductor substrate, and current flows in the channel region in the second direction parallel to the principal surface. Thus, because the channel width is parallel to the depth direction of the substrate, the channel resistance can be lowered, and accordingly the ON resistance of the semiconductor device can be lowered.
Further, because each impurity concentration of the base region and the source region is uniform in both the first and second directions, a parasitic n-p-n transistor that is constructed of the source region, the base region, and the drain region becomes less liable to be turned ON, and a depletion layer is suppressed from extending to make occurrence of punch-through difficult. The drain region may extend from the principal surface in the first direction, and otherwise, may be provided at the side of the back surface of the semiconductor substrate.